A systematic design methodology which maps a matrix multiplication algorithm into fault tolerant systolic array is presented. The procedure used to obtain fault tolerant space-time optimal systolic array is an improved version of the data dependence method for designing of systolic arrays combined with Algorithm Based Fault Tolerance (ABFT) technique. The ABFT technique is used to detect and correct transient hardware faults. By the encoding scheme and preserving property of the matrix arithmetic, the resultant erroneous data produced by the faulty processing element can be detected and corrected.