With the rapid development of VLSI (Very Large Scale Integration) circuit, IP (Intellectual Property) protection for reused technology is widely concerned. A watermarking scheme for IP protection is proposed on basis of a two dimensional chaotic mapping model (TDCM). The scheme utilizes a secure and controllable embedding model to compute the aggregation level of physical resource positions and the secure threshold of controllability. A two dimensional chaotic sequence is generated with the control of secure threshold. The first dimensional sequence is used to determine random watermark positions and the second dimensional sequence is to control watermark number in each position. Finally, the watermarks are inserted into corresponding places orderly. The experiments show that the proposed scheme has low resource overhead by comparing with other schemes. The resistance to attacks and robustness of the watermark are encouraging as well.