The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the representation of the function of the circuit. The faults are considered on the inputs and on the outputs of the model only. The random input stimuli are generated and selected then according to the proposed approach. The experimental results demonstrate the superiority of the delay test stimuli generated at the functional level using the introduced approach against the transition test stimuli obtained at the gate level by deterministic test generator. The functional delay test generation approach especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.